1. Field of the Invention
The present invention relates generally to the manufacture of semiconductor memory devices and, more particularly, to the formation of memory cells having active areas of reduced cross-sectional size.
2. Background of the Related Art
Memory devices are integrated circuits that store information, typically for use by a microprocessor. A memory device can have a plurality of memory arrays, and each memory array can include hundreds of thousands of memory cells. Each memory cell generally includes a memory element and an access device coupled to the memory element. The memory cell may store information by storing a charge or by changing resistivity.
Chalcogenide materials recently have been proposed to form memory elements in memory devices. Chalcogenides are materials which may be electrically stimulated to change states, from an amorphous state to a crystalline state, for example, or to exhibit different resistivities while in the crystalline state. Thus, chalcogenide memory elements can be utilized in memory devices for the storage of binary data, and the storage of data represented in higher-based systems has also been proposed. Such memory cells may be accessed by applying a voltage potential across selected word lines and digit lines, in a manner similar to that conventionally utilized in memory devices. In one exemplary implementation suitable for use in a RAM, the access device may be a diode.
U.S. Pat. No. 5,335,219 is believed to be generally illustrative of the existing state of the art relative to chalcogenide materials, and it is believed to provide explanations regarding the current theory of function and operation of chalcogenide elements and their use in memory cells. The specification of U.S. Pat. No. 5,335,219 to Ovshinsky et al., issued Aug. 2, 1994, is incorporated herein by reference, for all purposes.
An observed property of a chalcogenide element in a memory cell is that the chalcogenide element will have an "active area" which may be less than the area of the entire chalcogenide element. The size of this active area can be controlled by controlling the size of electrodes that contact each side of the chalcogenide element or by controlling the size of the chalcogenide element itself. A primary reason for limiting the active area of a memory element is that, since the chalcogenide memory elements depend on current density to change states, the size of the active area is directly related to the programming current and/or time required to achieve the desired state change. Thus, in the interest of optimally fast programming rates of a memory device, it is desirable to minimize the dimensions of the active area.
Conventional techniques for forming the memory element and the electrode have included forming an aperture or cavity in a dielectric layer, and then depositing a conductive material (for the electrode) or an active material (for the memory element) in the aperture. Techniques for forming the aperture have included the application of a high current pulse to open a hole having a diameter on the order of 0.1 to 0.2 microns. Additional proposals have been made to utilize small-feature photolithography or etching techniques to establish an opening through the dielectric layer. Apertures having diameters of less than 0.2 microns can be formed photolithographically, but only with great difficulty. All of these methods suffer from technological constraints upon the aperture size, and they may offer less than optimal repeatability.
Co-pending patent application Ser. No. 08/486,635, describes a novel method for the formation of small electrodes. The method includes the use of a cylindrically shaped spacer to reduce the cross-sectional area of the electrode aperture, thereby minimizing the contact area of the electrode and the active area of the memory element. Under this method, the actual value of the cross-sectional area of the electrode depends both on the accuracy of the initial hole size and the accuracy of the sidewall spacer deposition. An alternative approach would be desirable which would facilitate forming a memory element while minimizing the relevance of such processing constraints.
The present invention may be directed to one or more of the concerns discussed above.